Non-volatile memory is a type of memory that preserves data with or without power applied to the memory. Most computer and electronic systems use a binary number system with bits stored in a non-volatile memory. Two distinctly different current levels that flow through the memory under the correct conditions represent each bit, which may be represented by a one or a zero.
Some memory is single-level, where one bit of information is stored in each memory cell. In order to determine the value of the memory cell, current through the memory cell is compared to a reference cell. A current through the memory cell that is higher than that through the reference cell represents one bit value (e.g., the number one), while a current through the memory cell that is lower than that through the reference cell represents the other bit value (e.g. the number zero).
Other memory is multi-level, having more than one bit in each memory cell. Multiple bits require more than two levels of current to represent the bits, further reducing the margin for error in reading memory cells. The margin for error is more limited in multi-level memory than in single-level memory.
FIG. 1A illustrates a conventional circuit for a matrix array of M rows and P bit lines (M and P being integers). Matrix memory array 1 includes an array of M×P cells, which during a read operation row decoder 2 selects word line WLS 3. Column decoder and polarization circuit 4 selects bit lines BL1-BLN 5, for N total cells 6 (N being an integer). All selected cells 6 belong to the same word line 3 and each have their own bit line 5.
Reference word lines 7 select a row of reference cells 8, while reference bit lines 9 from polarization circuit 11 select the column. Typically, reference word lines 7 are all at the same voltage level VXR, which is also the voltage for word line WLS 3. Reference bit lines 9 and bit lines 5 for the matrix memory array 1 are typically around 1V. Word lines 3 that are not active are held at 0V, while unselected bit lines 5 are floating. The voltage VXR applied to cells 6 is higher than the three reference cell's 8 threshold voltages.
The current in each of the N selected cells 6 is compared to one reference cell 8 in the case of a single bit memory cell, or to three reference cells 8 in the case of a two bit memory cell.
For a single bit memory cell, one reference cell is needed to distinguish two current values, defined by 0 and 1. When a selected cell 6 has a current value higher than the reference cell 8 divided by a factor R (ratio), then the selected cell 6 is holding a value of 1. Otherwise, selected cell 6 is holding a value of 0.
FIG. 1B is a graph illustrating voltage threshold distributions for matrix cells in a single bit memory. FIG. 1B is discussed in conjunction with FIG. 1A. A reference cell 8 has a threshold voltage (Vtr) 13 at which it activates. In order to read on the gate of a selected cell 6 and/or a reference cell 8, a voltage VXR read 15 must be higher than the threshold voltage Vtr 13. For each read, N different cells 6 are selected while the same reference cell 8 is always polarized. If the current (or its ratio/multiple) read from a memory cell is above the reference cell, then the value in the memory cell is 1, otherwise it is 0.
In a two-bit matrix cell, three read reference cells are used to distinguish between four different current states called 11, 10, 01, and 00. Each memory cell can have four different current values. Current values correspond to threshold values. In the case of a two-bit memory cell, there are four threshold distributions that represent the four current states, distributed around the three reference cells (see FIG. 2) during ‘modify’ operations.
For example, FIG. 1C illustrates a simplified conventional memory circuit 10. Memory cells 12-1 through 12-n (collectively referred to as memory cells 12) are connected through drain polarization circuits 14-1 through 14-n (collectively referred to as polarization circuits 14) to current comparison circuit 16. Three reference cells 18A, 18B, 18C (collectively referred to as reference cells 18) make up a reference cell matrix for a two-bit memory cell. During a memory read, an enable signal is sent to drain polarization 14, while a voltage VXR is applied to the gate of memory cell 12 by a row decoder (not shown). Id13 cell current flows through memory cells 12 and drain polarization circuits 14. Reference cells 18 have their gates brought to voltage VXR, while an enable signal is sent to drain polarizations 20A, 20B, and 20C (collectively referred to as drain polarizations 20). Different currents (Id13 ref1, Id13 ref2 and Id13 ref3) flow through reference cells 18. Current comparison circuit 16 compares the different currents to each Id13 cell current of the selected cell (flowing through memory cells 14) and determines to which of the four different current states Id13 cell current belongs for each matrix selected cell. Based on the results of the comparison, the current comparison circuit 16 makes a determination about the two-bit value stored in each of memory cells 12. The value may be one of 00, 01, 10, or 11, in a two-bit cell.
In order to turn on all the reference cells 18, a sufficiently high voltage VXR must be used, for example 5.75-6V, which is about 1V higher than in a single bit memory. FIG. 2 is a graph illustrating voltage threshold distributions for matrix cells in multilevel memory. VXR 30 is the voltage level typically applied to the gates of memory cells 12 and all of reference cells 18 in FIG. 1C. Four matrix cell distributions are in a two-bit memory cell, namely 11, 10, 01, and 00, determined in a modify operation. The three read reference voltage thresholds are Vtr1 32A, Vtr2 32B, and Vtr3 32C. VXR in FIG. 1C should be high enough to turn on all of reference cells 18, and high enough to supply current in order to read the cells within the time allotted. Higher voltage levels improve current comparison circuit 16 access and read times, however if it is too high then selected reference and memory cells may be soft-programmed or soft-written. High gate voltage and a polarized drain may result, particularly in an erased cell being soft-written. This will cause false reads from the memory cell.
With a high voltage level VXR 30, it is possible to move the threshold voltage of reference cells 18 upward, including cells of distributions 11, 10, and 01, especially reference cell 18A and matrix cells belonging to low threshold distribution 11, which have the lowest voltage threshold level. Furthermore, the space between the distribution of voltage threshold levels, and space between the read reference thresholds and matrix cell threshold distributions may decrease, also causing memory read fails if current comparison circuit 16 could be unable to differentiate between the cells.
The distance between matrix cell distributions and reference thresholds defines the read error margin. So that if, for example, reference cell VTR1, after several reads, is soft-written, the margin to correctly read a cell belonging to distribution 10 is reduced.
While important in single-level memory, the problem of soft-writing becomes significant in multi-level memory due to the decreased space between voltage thresholds. The higher gate voltage necessary to activate a greater number of cells than in a two-bit memory compounds the problem.
Accordingly, what is needed is a system and method for reducing soft-writing in reference cells and matrix cells in a multi-level flash memory. The present invention addresses such a need.